Simulation of computer architectures has made rapid progress recently. The primary application areas are hardware/software performance estimation and optimization as well as functional and timing verification. Recent innovative technologies such as retargetable simulator generation dynamic binary translation or sampling simulation have enabled widespread use of processor and system-on-chip (SoC) simulation tools in the semiconductor and embedded system industries. Simultaneously processor and SoC simulation is still a very active research area e.g. what amounts to higher simulation speed flexibility and accuracy/speed trade-offs. This book presents and discusses the principle technologies and state-of-the-art in high-level hardware architecture simulation both at the processor and the system-on-chip level.